DRAM Retention Behavior with Accelerated Aging in Commercial Chips

The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing significant threat if employed critical infrastructure. In this work, we look at retention behavior commercial DRAM chips from real-time silicon measurements investigate how reliability with accelerated aging. We analyze retention-based errors three different aging points observe design-induced variations, pattern dependency, explore impacts for multiple vendors. also chips’ statistical distribution attribute vital wear-out effects present DRAM. see continuous increase error age therefore infer that signatures can be used differentiate recycled chain. discuss roles device signature aging-related implication row-hammer error.